EDN

Aldec granted new patent on automatic ASIC prototyping

Aldec, Inc., which specializes in in mixed-language simulation, hardware accelerators, and prototyping tools has been awarded a new US Patent for the automatic conversion of ASIC designs into FPGA ...
Business Wire

Aldec Sets a New Paradigm with a Single Platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017 ...
Design-Reuse

Aldec's HES UltraScale+ Reconfigurable Accelerator and Northwest Logic's PCI Express Cores Provide Proven PCI Express Solution

Henderson, NV. – April 11th, 2018 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has used Aldec’s HES-XCVU9P-QDR UltraScale+ ...
Business Wire

Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a leader in RTL simulation and Electronic Design Automation (EDA), unveils a new low-cost mixed language RTL simulator -- Active-HDL™ Designer Edition.
Design-Reuse

Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification

Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...
New Electronics

Aldec releases latest version of the Riviera-PRO

Aldec has said that it is now supplying the most comprehensive implementation of VHDL 2019 for both Windows and Linux platforms with the latest release of Riviera-PRO (release version 2021.04).
EDN

Aldec asks federal court to recall Xilinx software

SAN MATEO, Calif. — As part of an ongoing legal battle, Aldec Inc. has asked the San Francisco Federal Court to recall all design tools that Xilinx Inc. shipped to customers between 1996 and 2001 ...
New Electronics

Aldec adds UVM Generator to Riviera-PRO

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
Semiconductor Engineering

Virtual Modeling With Aldec And Imperas

How to simulate and debug virtual models of processors, memories and peripherals without slowing down the rest of the emulation process. Virtual platforms play a significant role in system level ...
Traders Magazine

FPGAs Can Help Latency Sensitive Traders Achieve Better Executions

In this Q&A with Traders Magazine, Louie De Luna, Director of Marketing at ALDEC, talks about trading technologies such as Field Programmable Gate Arrays, software and latency issues and how his firm ...
Electronics Weekly

Aldec enhances verification and validation tool

Aldec, the specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has enhanced its HES Proto-AXI software to provide greater support to ...
Semiconductor Engineering

Meanwhile, 35 Years Later…

At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35 th anniversary with a ...