Electronic Design

FPGA Design Suite Builds In Timing Analysis With Native Support For SDC Format

With FPGAs pushing aside ASICs in many complex designs, the limits of traditional FPGA timing-analysis tools are being stressed to the breaking point. So if you want to use today's high-end FPGAs in ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
EDN

FPGA IDE tool aids timing, power analysis

The Libero integrated design environment for Actel FPGAs offers advanced timing and power analysis functionalities, along with improved IP inclusion methods. The enhanced SmartPower tool enables ...
Yahoo Finance

New Software From Plunify Solves FPGA Timing, Optimization Issues

SAN FRANCISCO, CA--(Marketwired - Jun 2, 2014) - The who's who of the chip design community will be in San Francisco this week for DAC, and new ideas, trends and technologies will be the talk of the ...
EDN

Advancing FPGA design flows using Chronology’s TimingDesigner

When combined with advances in FPGA technologies that ease complex interface design efforts, Chronology's TimingDesigner can simplify design issues and provide advanced accurate control of high-speed ...
Electropages

PCIe 4xLIN introduced for next-level LIN connectivity

The interface provides four individually galvanically isolated LIN channels through a single PCIe card. FPGA-based Kvaser LIN-IP technology enables communication up to 20kbaud with 1µs timestamp ...
Electronic Design

Improve Logic Timing with Worst-Case Analysis

Worst-case circuit analysis (WCCA) is a cost-effective means of screening a design to verify with a high degree of confidence that potential defects and deficiencies are identified and eliminated ...
Design-Reuse

FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions

In the nanometer era, complex SoCs have higher risk of re-spins. Undoubtedly FPGA prototyping is the right way of pre-silicon SoC validation, accelerate system software development and to meet time-to ...
Design-Reuse

Learning to Share - Embedded FPGA Timing Closure

When we start school as young children, one of the first lessons we learn is how to share (followed quickly by not running with scissors). As our Sr. Director of Systems Engineering, Kent Orthner, ...
Electronics Weekly

Timing closure on complex FPGA designs

Whack-a-Mole is an old (pre-electronic) arcade game where moles randomly pop out of holes. The aim is to hit each mole with a mallet, causing it to retreat and earning you points. I should point out ...