When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...
Recently we’ve seen some tremendous momentum around Assertion-Based Verification (ABV) methodologies and standards. These newer methods and standards have enabled design and verification engineers to ...
Power domains are required in the design due to stringent active and standby power specifications. Depending upon various modes of operation of a chip, power domains allow parts of a chip to be ...
A new technical paper titled “A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level” was this year’s first place winner of Intel’s Hardware Security Academic Award ...
Formal architectural verification also makes it possible to tune flow-control parameters, such as how many credits each agent should have, and thus optimize design throughput. A technology provided by ...
As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
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