As total system complexity grows, so does verification complexity. To speed simulation time and improve functional coverage of the RTL ASIC under test, the transactors used for RTL verification must ...

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...

San Mateo, Calif. – As the size of the verification problem in system-on-chip design has become apparent, design teams have been throwing any resources they can lay their hands on at the problem.

Doubling the performance of the previous release, Version 6.2 of Active-HDL is an integrated, Windows-based HDL design and simulation environment. Behavioral, gate-level, and timing simulation ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...

Before a chip design is turned from a hardware design language (HDL) like VHDL or Verilog into physical hardware, testing and validating the design is an essential step. Yet simulating a HDL design is ...

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...