Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
EDN

FPGA-based simulator mimics CameraLink cameras

Supplier of FPGA-based compute accelerator systems GiDEL has announced their new PROC_CamSim product that can automatically generate CameraLink images during image and vision system development ...
Seeking Alpha

WiMi Develops a Hybrid CPU-FPGA Quantum AI Simulator

BEIJING, Jan. 14, 2025 /PRNewswire/ -- WiMi Hologram Cloud Inc. (WIMI) ("WiMi" or the "Company"), a leading global Hologram Augmented Reality ("AR") Technology provider, today announced the ...
manilatimes

MicroCloud Hologram Inc. Develops Serial-Parallel Architecture-Based FPGA Quantum Computing Simulation Framework

SHENZHEN, China, Dec. 22, 2025 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO” or the "Company"), a technology service provider, launched a brand-new FPGA-based quantum computing ...
Yahoo Finance

MicroCloud Hologram Inc. Builds the Industry's First Multi-FPGA Quantum Fourier Transform Simulation Solution

SHENZHEN, China, Jan. 8, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, launched a brand-new scalable quantum Fourier transform ...
Business Wire

Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a leader in RTL simulation and Electronic Design Automation (EDA), unveils a new low-cost mixed language RTL simulator -- Active-HDL™ Designer Edition.
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
Semiconductor Engineering

Hardware-Accelerated RTL Simulator

A technical paper titled “Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism” was published by researchers at EPFL, University of Tokyo, Sharif University, and ...
EDN

FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs

ASIC designs continue to increase in size, complexity, and cost (for the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices). At the same time, aggressive ...
Design-Reuse

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

The latest release of HES-DVM™ provides a simulation acceleration flow, providing significant RTL simulation speed-up of designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 ...