Design-Reuse

DDR SDRAM Controller IP Designed for Reuse

This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. The development of integrated systems-on-a-chip (SoC) is based ...
Design-Reuse

Design and Implementation of SD Host Controller IP Core

This paper discusses a method to design an SD Host Controller IP Core that can be implemented on FPGAs. FPGAs are being widely deployed in various applications including industrial, commercial and ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...