EDN

How to build reliable FPGA memory interface controllers without writing your own RTL code!

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs ...
EDN

Recycle RTL test benches to verify Transaction-Level IP Models

System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
Electronic Design

MoSys’ Graph Memory Engine Accelerator IP Targets Packet Classification on Intel’s Stratix 10 FPGAs

The GME product offering includes software, firmware and RTL and utilizes a common API and common RTL interface to facilitate platform portability. MoSys announced that its Graph Memory Engine (GME) ...
Electronic Design

Navigating the Hardware-Software Interface in Chip Design

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...