System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to ...

In the context of todays increasingly complex SoC's there is a need for design methodologies that start at higher levels of abstraction. Transactional modeling can become this new abstraction level.

San Jose, CA / Santa Clara, CA – SmartDV and Mirabilis Design today announced a strategic collaboration to deliver system-level models of SmartDV IP, enabling SoC architects and system designers to ...

Experts at the Table, part one: Where the holes are showing up in tools and flows for advanced designs. Not all vendors or tools play nicely together, and no one really knows what’s going to happen ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...