EDN

SoC test requirements debated

BALTIMORE — The prevalence and escalating cost of system-on-chip (SoC) designs are forcing a reexamination of existing approaches to design and test, according to EDA and test industry executives at a ...
EDN

Indian researchers propose new SoC test method

BANGALORE, India — With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test ...
Seeking Alpha

iTest Selects Advantest V93000 EXA Scale™ SoC Test System

TOKYO, Oct. 11, 2023 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today announced that IC testing laboratory iTest, Inc. has taken a delivery of ...
Semiconductor Engineering

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...
Electronic Design

SoC Test Platform Speeds Time-To-Volume

The Octet configurable system-on-a-chip (SoC) platform from Credence Systems combines a comprehensive software package and built-in flexibility to speed time-to ...
Electronic Design

Tackling Next-Generation RF SOC Test

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...