Phys.org

PVA Tepla, imec demonstrate 3D through-silicon via (TSV) void detection using GHz scanning acoustic microscopy

Imec and PVA Tepla present breakthrough results in the detection of TSV voids in 3D stacked IC technology. After having applied Scanning Acoustic Microscopy to temporary wafer (de)bonding inspection, ...
Electronics Weekly

Imec and SPTS join on TSV

Imec and SPTS Technologies are developing a short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in ...
Electronics Weekly

Imec and Sony develop backside interconnect integration module

Imec and Sony have developed a novel integration module for highly dense backside interconnects – key components of 3D stacking and backside functionalisation technologies. The module is structured ...
Electronic Design

PVA Tepla and Imec Demonstrate 3-D TSV Void Detection using GHz SAM

January 21, 2013. Imec and PVA Tepla have presented results regarding the detection of TSV voids in 3-D stacked IC technology. After having applied scanning acoustic microscopy (SAM) to temporary ...
Science Daily

Significant Process In Creating 3D Stacked Integrated Chips

A nanoelectronics research institute has announced that it has made significant progress with its 3D-SIC (3D stacked IC) technology. Scientists recently demonstrated the first functional 3D integrated ...
Nanowerk

Novel 3D integration process flow: backside 'soft' via reveal

(Nanowerk News) Imec presents a via-middle through-Si-via (TSV) approach to 3D stacking. This method is new to industry as it allows to 'reveal' TSV contacts by using a Si-etch process. The process ...
EE Herald

Detection of TSV voids in 3D stacked IC using acoustic microscopy

Semiconductor technology researcher Imec and PVA Tepla have annonuced breakthrough results in the detection of Through Silicon Vias (TSV) voids in 3D stacked IC technology. After having applied ...
New Electronics

Sony and imec develop high-density backside interconnect technology for 3D chips

Sony Semiconductor Solutions and research institute imec have announced a new integration approach designed to improve the ...
Digi Times

Imec, Sony unveil backside interconnect method for 3D chip stacking

Imec and Sony Semiconductor Solutions Corporation (Sony) have jointly presented a new integration method for connecting the front and back sides of semiconductor wafers, a step the two organizations ...
EDN

IMEC demonstrates 3D stacked integrated circuits IMEC Annual Research Review Meeting

Leuven, Belgium – October 13, 2008 – IMEC, Europe’s leading independent nanoelectronics research institute today announced that it has made significant progress with its 3D-SIC (3D stacked IC) ...
Electronic Design

Imec Teams With Cadence on DFT Solution for 3-D Memory-on-Logic

January 25, 2013. At the European 3D TSV Summit in Grenoble, France, on January 22-23, 2013, imec announced that together with Cadence Design Systems they have developed, implemented, and validated an ...
Nanowerk

IMEC demonstrates 3D stacked integrated circuits

(Nanowerk News) IMEC, Europe’s leading independent nanoelectronics research institute today announced that it has made significant progress with its 3D-SIC (3D stacked IC) technology. IMEC recently ...