Yahoo Finance

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

ALAMEDA, CA--(Marketwired - Aug 5, 2014) - Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
EDN

VHDL International Sets Foundation for System-Level Design

Indications are strong that theelectronics industry is indeed inching toward a higher level ofabstraction and system-level design. The most noticeable are thenumber of design language proposals from ...
Semiconductor Engineering

Sigasi: Cleaner VHDL And SystemVerilog

Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary to get products right prior to ...
EDN

Ansoft Certifies the Automotive Industry Standard VHDL-AMS Models for Use with Simplorer Multi-Domain System Simulator

PITTSBURGH – November 1, 2007 – Ansoft Corporation (NASDAQ: ANST) has certified the VHDL-AMS models available from the FAT-AK30 working group of the German Association of the Automotive Industry ...
Design-Reuse

So-ADE Unveils Debugger for Use with Verific Design Automation's SystemVerilog, VHDL, UPF Parser Platforms

Saint Geoire En Valdaine, France -- May 21, 2015-- So-ADE today announced immediate availability of an easy-to-use and intuitive debugger for the development and debugging of the SystemVerilog, VHDL ...